Shanghai, China, July 23, 2021-Kadence Electronics (Cadence, USA, NASDAQ: CDNS) today announced the launch of Cadence® CerebrusTM Intelligent Chip Explorer-the first innovative machine learning (ML)-based design tool that can be expanded The digital chip design process and automate it, allowing customers to efficiently achieve demanding chip design goals. Cerebrus and Cadence RTL-to-signoff process are combined to provide support for high-end process chip designers, CAD teams, and IP developers. Compared with manual methods, engineering productivity can be increased by up to 10 times, and at the same time, the work can be increased by up to 10 times. Consumption, performance and area (PPA) results have improved by 20%.

With the addition of Cerebrus to Cadence’s extensive digital product series, Cadence can now provide the industry’s most advanced machine learning-based digital full process, from synthesis to implementation and sign-off. This new tool has cooperated with a number of leading cloud service providers to enable cloud computing services, which can utilize highly scalable computing resources to quickly meet the design requirements of a wide range of markets including consumer electronics, hyper-scale computing, 5G communications, automotive and mobile. For more information about Cerebrus, please visit www.cadence.com/go/cerebruspr.

Cerebrus brings the following advantages to customers:

·Enhanced machine learning: Quickly find process solutions that engineers might not try or explore, improving PPA and productivity.

·Machine learning model reuse: Allows the design learning experience to be automatically applied to future designs, shortening the time to obtain better results.

·Improve productivity: Let an engineer automatically optimize the complete RTL-to-GDS process for multiple blocks at the same time to improve the work efficiency of the entire design team.

·Large-scale distributed computing: Provide scalable local or cloud-based design exploration to achieve faster process optimization.

·Easy-to-use interface: powerful user management tools that support interactive result analysis and operation management to gain in-depth understanding of design indicators.

“Prior to this, there was no automated way to help the design team reuse the design knowledge accumulated in the past. Each new project would have to spend too much time on experience learning again, which would also affect the profitability of the project.” Dr. Chin-Chi Teng, senior vice president and general manager of the Digital and Sign-off Division of Cadence, said, “The launch of Cerebrus marks the EDA industry has ushered in a disruptive innovation. The digital chip design tools centered on machine learning will Give engineering teams more opportunities to exert greater influence in projects, because they can say goodbye to repetitive manual processes. As the industry continues to develop toward advanced process nodes, and the design scale and complexity continue to increase, Cerebrus can help designers Achieve PPA goals more effectively.”

Cerebrus is a part of the wider Cadence digital full process, which can be combined with Genus™ Synthesis Solution, Innovus™ Implementation System design and implementation system, Tempus™ Timing Signoff Solution timing signoff solution, Joules™ RTL Power Solution, Voltus™ IC Power Integrity Solution IC’s power integrity solution and Pegasus™ Verification System tool platforms seamlessly integrate and cooperate to provide customers with rapid design closure and better predictability. This new tool and wider design process support Cadence’s Intelligent System Design™ strategy, which aims to drive pervasive intelligence and achieve superior design.

client feedback

“In order to maximize the effective use of the latest process nodes to create new designs, our engineering team needs an advanced digital design implementation process that is continuously developed. For more efficient product development, the automatic optimization of the design implementation process has become critical. Cerebrus relies on its innovative machine learning capabilities, equipped with Cadence RTL-to-signoff tool process, can provide automated process optimization and layout planning optimization, and improve design performance by more than 10%. In view of the successful experience of the project, we will develop in the latest design project The tool process is adopted in China.”

– Satoshi Shibatani, Director of Digital Design Technology, Renesas Shared R&D EDA Department

“As Samsung Foundry continues to deploy the most advanced process nodes, it is very necessary to ensure that our Design Technology Collaborative Optimization (DTCO) program is carried out efficiently. We are always looking for innovative ways to exceed PPA goals in chip implementation. As we work with As part of Cadence’s long-term cooperation, Samsung Foundry has used Cerebrus and Cadence’s digital design implementation process in a number of applications. Among them, some very critical modules have reduced power consumption by more than 8% in just a few days. In the past, it took several months to achieve through manual operation. In addition, we are using Cerebrus for automatic layout planning and power distribution network selection, which has increased the final design timing by more than 50%. Because of Cerebrus and the digital implementation process provide better With its PPA results and significant productivity gains, this solution has become a valuable addition to our DTCO program.”

– Sangyun Kim, Vice President of Design Technology, Samsung Foundry

Shanghai, China, July 23, 2021-Kadence Electronics (Cadence, USA, NASDAQ: CDNS) today announced the launch of Cadence® CerebrusTM Intelligent Chip Explorer-the first innovative machine learning (ML)-based design tool that can be expanded The digital chip design process and automate it, allowing customers to efficiently achieve demanding chip design goals. Cerebrus and Cadence RTL-to-signoff process are combined to provide support for high-end process chip designers, CAD teams, and IP developers. Compared with manual methods, engineering productivity can be increased by up to 10 times, and at the same time, the work can be increased by up to 10 times. Consumption, performance and area (PPA) results have improved by 20%.

With the addition of Cerebrus to Cadence’s extensive digital product series, Cadence can now provide the industry’s most advanced machine learning-based digital full process, from synthesis to implementation and sign-off. This new tool has cooperated with a number of leading cloud service providers to enable cloud computing services, which can utilize highly scalable computing resources to quickly meet the design requirements of a wide range of markets including consumer electronics, hyper-scale computing, 5G communications, automotive and mobile. For more information about Cerebrus, please visit www.cadence.com/go/cerebruspr.

Cerebrus brings the following advantages to customers:

·Enhanced machine learning: Quickly find process solutions that engineers might not try or explore, improving PPA and productivity.

·Machine learning model reuse: Allows the design learning experience to be automatically applied to future designs, shortening the time to obtain better results.

·Improve productivity: Let an engineer automatically optimize the complete RTL-to-GDS process for multiple blocks at the same time to improve the work efficiency of the entire design team.

·Large-scale distributed computing: Provide scalable local or cloud-based design exploration to achieve faster process optimization.

·Easy-to-use interface: powerful user management tools that support interactive result analysis and operation management to gain in-depth understanding of design indicators.

“Prior to this, there was no automated way to help the design team reuse the design knowledge accumulated in the past. Each new project would have to spend too much time on experience learning again, which would also affect the profitability of the project.” Dr. Chin-Chi Teng, senior vice president and general manager of the Digital and Sign-off Division of Cadence, said, “The launch of Cerebrus marks the EDA industry has ushered in a disruptive innovation. The digital chip design tools centered on machine learning will Give engineering teams more opportunities to exert greater influence in projects, because they can say goodbye to repetitive manual processes. As the industry continues to develop toward advanced process nodes, and the design scale and complexity continue to increase, Cerebrus can help designers Achieve PPA goals more effectively.”

Cerebrus is a part of the wider Cadence digital full process, which can be combined with Genus™ Synthesis Solution, Innovus™ Implementation System design and implementation system, Tempus™ Timing Signoff Solution timing signoff solution, Joules™ RTL Power Solution, Voltus™ IC Power Integrity Solution IC’s power integrity solution and Pegasus™ Verification System tool platforms seamlessly integrate and cooperate to provide customers with rapid design closure and better predictability. This new tool and wider design process support Cadence’s Intelligent System Design™ strategy, which aims to drive pervasive intelligence and achieve superior design.

client feedback

“In order to maximize the effective use of the latest process nodes to create new designs, our engineering team needs an advanced digital design implementation process that is continuously developed. For more efficient product development, the automatic optimization of the design implementation process has become critical. Cerebrus relies on its innovative machine learning capabilities, equipped with Cadence RTL-to-signoff tool process, can provide automated process optimization and layout planning optimization, and improve design performance by more than 10%. In view of the successful experience of the project, we will develop in the latest design project The tool process is adopted in China.”

– Satoshi Shibatani, Director of Digital Design Technology, Renesas Shared R&D EDA Department

“As Samsung Foundry continues to deploy the most advanced process nodes, it is very necessary to ensure that our Design Technology Collaborative Optimization (DTCO) program is carried out efficiently. We are always looking for innovative ways to exceed PPA goals in chip implementation. As we work with As part of Cadence’s long-term cooperation, Samsung Foundry has used Cerebrus and Cadence’s digital design implementation process in a number of applications. Among them, some very critical modules have reduced power consumption by more than 8% in just a few days. In the past, it took several months to achieve through manual operation. In addition, we are using Cerebrus for automatic layout planning and power distribution network selection, which has increased the final design timing by more than 50%. Because of Cerebrus and the digital implementation process provide better With its PPA results and significant productivity gains, this solution has become a valuable addition to our DTCO program.”

– Sangyun Kim, Vice President of Design Technology, Samsung Foundry

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